The present invention relates to a process for integrating in a same chip a non-volatile memory and a high-performance circuitry.
The evolution of integration technologies aiming at the formation of whole electronic systems or subsystems on a single semiconductor chip involves the capability of combining a logic circuitry with memories having a high degree of complexity.
In particular there is an increasing demand for the integration of non-volatile memories, particularly of the Flash EEPROM type, in CMOS manufacturing processes for logic circuitries of high performance.
This kind of combination becomes more and more difficult, from a technical viewpoint, due to the different requirements in terms of operating voltages.
The natural evolution of CMOS processes for high-performance logic circuitries is leading to a reduction of the operating voltage so to allow scaling of transistors"" size; the shrinking and operating voltage reduction determine a corresponding reduction of the transistors"" gate oxide thickness and junction depth.
On the other hand, non-volatile memories require relatively high programming voltages, and the values of such voltages are not expected to significantly decrease in the coming future, at least as far as floating-gate non-volatile memories are concerned.
Considering by way of example a 0.25 xcexcm technology, transistors obtained by means of a CMOS process devised for high-performance logic circuitries are optimized for operating in a voltage supply value range of 0.9-2.5 V; these transistors have a gate oxide approximately 5 nm thick, and source/drain junctions capable of withstanding a voltage not higher than 8-10 V.
On the contrary, a Flash EEPROM memory requires a programming voltage in the range of 10-12 V (the programming voltage is even higher for other kinds of non-volatile memories); transistors capable of withstanding these voltages must have gate oxides with a thickness in the range 15-18 nm, and source/drain junctions with a breakdown voltage higher than the programming voltage.
It is not easy to conciliate these contrasting needs. From the one hand, any attempt to modify the structure of the transistors of an advanced CMOS process to make them capable of withstanding the relatively high voltages required by non-volatile memories results in an unacceptable degradation of the performance of the logic circuitry. On the contrary, the complete duplication of the peripheral structures for obtaining both high-performance CMOS transistors and transistors capable of sustaining high voltages greatly increases the number of masks of the manufacturing process.
A process for the manufacturing of Flash EEPROM memories of relatively high density (i.e., greater than 256-512 Kbits) requires two polycrystalline silicon layers, the lower one (xe2x80x9cfirst polyxe2x80x9d) used for forming the floating gates of the memory cells, the upper one (xe2x80x9csecond polyxe2x80x9d) used for forming both the control gates of the memory cells and the gates of transistors. This process additionally requires at least two different thin oxide layers: one, with thickness of about 10 nm, is formed between the substrate surface and the lower polysilicon layer, works as a gate oxide for the memory cells; the other one, with thickness higher than 15 nm, is formed between the substrate and the upper polysilicon layer and forms the gate oxide of the transistors.
In some manufacturing processes, in order to improve the memory device performance at low voltages, transistors with a thin gate oxide (7-10 nm) are also provided; such transistors have a gate electrode formed from the second poly. However, in order to minimize the required number of additional masks, these transistors with thin gate oxide shares several structural elements with the transistors of thicker gate oxide for handling the relatively high voltages.
When it is desired to integrate a non-volatile memory, for example a Flash EEPROM memory, by means of advanced CMOS manufacturing processes, the features of the high-performance transistors must be preserved. To do this, the high-performance transistors cannot share common structural elements with the transistors for handling the relatively high voltages required by the memory cells. So, it is not sufficient to provide for the formation of two different gate oxides, and one or two masks for adjusting the threshold voltages. Extra masks would be needed to provide ad-hoc high-voltage source and drain junctions for high voltage transistors, and then the number of additional masks could easily become excessively high.
In view of the state of the art described, it is an object of the present invention that of providing a process for integrating in a same chip a non-volatile memory and a high-performance logic circuitry.
According to an embodiment of the present invention, this object has been achieved by means of a process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than said low operating voltage of the logic circuitry. The process includes:
on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at said high operating voltage;
on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device;
on said first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells;
forming over the floating-gate electrodes of the memory cells a dielectric layer;
on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at said low operating voltage;
on the dielectric layer and on said third portions of the semiconductor substrate, forming from a second polysilicon layer control gate electrodes for the memory cells, and gate electrode for the second transistors;
in said first portions of the semiconductor substrate, forming source and drain regions for the first transistors;
in said second portions of the semiconductor substrate, forming source and drain regions for the memory cells;
in said third portions of the semiconductor substrate, forming source and drain regions for the second transistors.